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M41T81S
Serial access real-time clock with alarms Features
Counters for tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, year, and century 32KHz crystal oscillator with integrated load capacitance (12.5pf) which provides exceptional oscillator stability and high crystal series resistance operation) Oscillator stop detection (monitors clock operation) Serial interface supports i2c bus (400kHz protocol) Ultra-low battery supply current of 0.6A (typ) 2.0 to 5.5v clock operating voltage Automatic switchover and deselect circuitry (fixed reference) which provides full operation in 3.0V applications) VCC = 2.7 to 5.5V 2.5V VPFD 2.7V Power-down time stamp (ht bit) which allows determination of time elapsed in battery backup Battery low flag Programmable alarm and interrupt function (valid even during battery back-up mode) Accurate programmable watchdog timer (from 62.5ms to 128s) Software clock calibration (to compensate for crystal deviation due to temperature) Operating temperature of -40 to 85C Package options include an 8-lead SOIC or 18lead embedded crystal SOIC
1
8 1

SO8 (M) 8-pin SOIC
18
SOX18 (MY) 18-pin (300mil) SOIC with Embedded Crystal

January 2007
Rev 5
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www.st.com 1
Contents
M41T81S
Contents
1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Acknowledge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power-down timestamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Clock registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Setting alarm clock registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Square wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Century bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Battery low warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Oscillator fail detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Oscillator fail interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Output driver pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Preferred initial power-on default . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4 5 6
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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M41T81S
Contents
7 8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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List of tables
M41T81S
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Clock register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Square Wave Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Preferred default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 SO8 - 8-lead plastic small outline (150 mils body width), package . . . . . . . . . . . . . . . . . . 27 SOX18 - 18-lead plastic small outline, 300mils, embedded crystal, . . . . . . . . . . . . . . . . . 28 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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M41T81S
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8-pin SOIC (M) connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 18-pin, 300mil SOIC (MY) connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Alternative READ mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 WRITE mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Alarm interrupt reset waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Back-up mode alarm waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SO8 - 8-lead plastic small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SOx18 - 18-lead plastic small outline, 300mils, embedded crystal, outline . . . . . . . . . . . . 28
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Summary description
M41T81S
1
Summary description
The M41T81S is a low power Serial RTC with a built-in 32.768kHz oscillator (external crystal controlled). Eight bytes of the SRAM (see Table 2: Clock register map on page 15) are used for the clock/calendar function and are configured in binary coded decimal (BCD) format. An additional 12 bytes of SRAM provide status/control of Alarm, Watchdog and Square Wave functions. Addresses and data are transferred serially via a two line, bi-directional I2C interface. The built-in address register is incremented automatically after each WRITE or READ data byte. The M41T81S has a built-in power sense circuit which detects power failures and automatically switches to the battery supply when a power failure occurs. The energy needed to sustain the clock operations can be supplied by a small lithium button supply when a power failure occurs. Functions available to the user include a non-volatile, time-ofday clock/calendar, Alarm interrupts, Watchdog Timer and programmable Square Wave output. The eight clock address locations contain the century, year, month, date, day, hour, minute, second and tenths/hundredths of a second in 24 hour BCD format. Corrections for 28, 29 (leap year - valid until year 2100), 30 and 31 day months are made automatically. The M41T81S is supplied in either an 8-pin SOIC or an 18-pin (MY), 300mil SOIC package which includes an embedded 32kHz crystal. The 18-pin, embedded crystal SOIC requires only a user-supplied battery to provide nonvolatile operation. Figure 1. Logic diagram
VCC VBAT
XI
(1) (1)
XO
M41T81S SCL SDA
IRQ/FT/OUT/SQW
VSS
AI09160
1. For SO8 package only
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M41T81S Table 1.
XI
(1)
Summary description Signal names
Oscillator Input Oscillator Output Interrupt / Output Driver / Frequency Test / Square Wave (Open Drain) Serial Data Input/Output Serial Clock Input Battery Supply Voltage Supply Voltage Ground No Connect No Function XO(1) IRQ/OUT/FT/SQW SDA SCL VBAT VCC VSS NC(2) NF(2)
1. For SO8 package only. 2. NC and NF pins should be tied to VSS.
Figure 2.
8-pin SOIC (M) connections
XI XO VBAT VSS
1 8 7 2 3 M41T81S 6 4 5
VCC (1) IRQ/FT/OUT/SQW SCL SDA
AI09161
1. Open drain output
Figure 3.
18-pin, 300mil SOIC (MY) connections
NC NF(1) (1) NF NC NC NC NC VBAT VSS
1 18 17 2 16 3 15 4 5 M41T81S 14 13 6 12 7 11 8 10 9
NC (1) NF (1) NF VCC NC IRQ/FT/OUT/SQW(2) NC SCL SDA
AI09162
1. NC and NF pins should be tied to VSS. Pins 2 and 3 are internally shorted together. Pins 17 and 16 are internally shorted together. 2. Open drain output
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Summary description Figure 4. Block diagram
M41T81S
REAL TIME CLOCK CALENDAR OSCILLATOR FAIL OFIE CIRCUIT CRYSTAL 32KHz OSCILLATOR RTC W/ALARM & CALIBRATION WATCHDOG I2C INTERFACE SQWE
(2)
AFE
SDA
IRQ/FT/OUT/SQW
(1)
SCL WRITE PROTECT
SQUARE WAVE
FREQUENCY TEST FT OUTPUT DRIVER OUT
INTERNAL POWER VCC
VBAT VSO VPFD
AI09163
COMPARE
1. Open drain output 2. Square Wave function has the highest priority on IRQ/FT/OUT/SQW output.
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M41T81S
Operation
2
Operation
The M41T81S clock operates as a slave device on the serial bus. Access is obtained by implementing a start condition followed by the correct slave address (D0h). The 20 bytes contained in the device can then be accessed sequentially in the following order: 1. Tenths/Hundredths of a Second Register 2. Seconds Register 3. Minutes Register 4. Century/Hours Register 5. Day Register 6. Date Register 7. Month Register 8. Year Register 9. Calibration Register 10. Watchdog Register 11 - 15. Alarm Registers 16. Flags Register 17 - 19. Reserved 20. Square Wave Register The M41T81S clock continually monitors VCC for an out-of-tolerance condition. Should VCC fall below VPFD, the device terminates an access in progress and resets the device address counter. Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from a an out-of-tolerance system. Once VCC falls below the switchover voltage (VSO), the device automatically switches over to the battery and powers down into an ultra-low current mode of operation to preserve battery life. If VBAT is less than VPFD, the device power is switched from VCC to VBAT when VCC drops below VBAT. If VBAT is greater than VPFD, the device power is switched from VCC to VBAT when VCC drops below VPFD. Upon power-up, the device switches from battery to VCC at VSO. When VCC rises above VPFD, it will recognize the inputs. For more information on Battery Storage Life refer to Application Note AN1012.
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a pull-up resistor. The following protocol has been defined:

Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is High. Changes in the data line, while the clock line is High, will be interpreted as control signals.
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Operation Accordingly, the following bus conditions have been defined:
M41T81S
Bus not busy
Both data and clock lines remain High.
Start data transfer
A change in the state of the data line, from high to Low, while the clock is High, defines the START condition.
Stop data transfer
A change in the state of the data line, from Low to High, while the clock is High, defines the STOP condition.
Data valid
The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with a ninth bit. By definition a device that gives out a message is called "transmitter," the receiving device that gets the message is called "receiver." The device that controls the message is called "master." The devices that are controlled by the master are called "slaves."
Acknowledge
Each byte of eight bits is followed by one Acknowledge Bit. This Acknowledge Bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable Low during the High period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case the transmitter must leave the data line High to enable the master to generate the STOP condition.
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M41T81S Figure 5. Serial bus data transfer sequence
Operation
DATA LINE STABLE DATA VALID
CLOCK
DATA
START CONDITION
CHANGE OF DATA ALLOWED
STOP CONDITION
AI00587
Figure 6.
Acknowledgement sequence
START SCL FROM MASTER 1 2 8 CLOCK PULSE FOR ACKNOWLEDGEMENT 9
DATA OUTPUT BY TRANSMITTER
MSB
LSB
DATA OUTPUT BY RECEIVER
AI00601
READ mode
In this mode the master reads the M41T81S slave after setting the slave address (see Figure 8 on page 12). Following the WRITE Mode Control Bit (R/W=0) and the Acknowledge Bit, the word address 'An' is written to the on-chip address pointer. Next the START condition and slave address are repeated followed by the READ Mode Control Bit (R/W=1). At this point the master transmitter becomes the master receiver. The data byte which was addressed will be transmitted and the master receiver will send an Acknowledge Bit to the slave transmitter. The address pointer is only incremented on reception of an Acknowledge Clock. The M41T81S slave transmitter will now place the data byte at address An+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to "An+2." This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume due to a Stop Condition or when the pointer increments to any non-clock address (08h-13h). Note: This is true both in READ Mode and WRITE Mode.
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Operation
M41T81S An alternate READ Mode may also be implemented whereby the master reads the M41T81S slave without first writing to the (volatile) address pointer. The first address that is read is the last one stored in the pointer (see Figure 9 on page 12). Figure 7. Slave address location
R/W
START
SLAVE ADDRESS
A
MSB
1
1
0
1
0
0
LSB 0
AI00602
Figure 8.
READ mode sequence
START START R/W R/W
BUS ACTIVITY: MASTER
SDA LINE
S
WORD ADDRESS (An) ACK
S
DATA n
DATA n+1
ACK
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
SLAVE ADDRESS STOP
DATA n+X
P
AI00899
Figure 9.
Alternative READ mode sequence
START STOP DATA n ACK ACK DATA n+1 ACK ACK DATA n+X P NO ACK
AI00895
BUS ACTIVITY: MASTER SDA LINE
S
BUS ACTIVITY: SLAVE ADDRESS
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R/W
NO ACK
ACK
M41T81S
Operation
WRITE mode
In this mode the master transmitter transmits to the M41T81S slave receiver. Bus protocol is shown in Figure 10 on page 13. Following the START condition and slave address, a logic '0' (R/W=0) is placed on the bus and indicates to the addressed device that word address "An" will follow and is to be written to the on-chip address pointer. The data word to be written to the memory is strobed in next and the internal address pointer is incremented to the next address location on the reception of an acknowledge clock. The M41T81S slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address see Figure 7 on page 12 and again after it has received the word address and each data byte.
Data retention mode
With valid VCC applied, the M41T81S can be accessed as described above with READ or WRITE Cycles. Should the supply voltage decay, the power input will be switched from the VCC pin to the battery when VCC falls below the Battery Back-up Switchover Voltage (VSO). At this time the clock registers will be maintained by the attached battery supply. On powerup, when VCC returns to a nominal value, write protection continues for tREC. For a further, more detailed review of lifetime calculations, please see Application Note AN1012. Figure 10. WRITE mode sequence
START
BUS ACTIVITY: MASTER
SDA LINE
S
WORD ADDRESS (An) ACK ACK
DATA n
DATA n+1
DATA n+X
P
ACK
ACK
BUS ACTIVITY: SLAVE ADDRESS
AI00591
ACK
STOP
R/W
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Clock operation
M41T81S
3
Clock operation
The 20-byte Register Map (see Table 2: Clock register map on page 15) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. Tenths/Hundredths of Seconds, Seconds, Minutes, and Hours are contained within the first four registers.
Note:
Tenths/Hundredths of seconds cannot be written to any value other than "00." Bits D6 and D7 of Clock Register 03h (Century/Hours Register) contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle. Bits D0 through D2 of Register 04h contain the Day (day of week). Registers 05h, 06h, and 07h contain the Date (day of month), Month and Years. The ninth clock register is the Calibration Register (this is described in the Clock Calibration section). Bit D7 of Register 01h contains the STOP Bit (ST). Setting this bit to a '1' will cause the oscillator to stop. If the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator restarts within one second. The eight Clock Registers may be read one byte at a time, or in a sequential block. Provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read. If a clock address is being read, an update of the clock registers will be halted. This will prevent a transition of data during the READ.
Power-down timestamp
When a power failure occurs, the HALT (HT) Bit will automatically be set to a '1.' This will prevent the clock from updating the registers, and will allow the user to read the exact time of the power-down event. Resetting the HT Bit to a '0' will allow the clock to update the registers with the current time.
Clock registers
The M41T81S offers 20 internal registers which contain Clock, Alarm, Watchdog, Flags, Square Wave and Calibration data. These registers are memory locations which contain external (user accessible) and internal copies of the data (usually referred to as BiPORTTM cells). The external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. The internal divider (or clock) chain will be reset upon the completion of a WRITE to any clock address. The system-to-user transfer of clock data will be halted whenever the address being read is a clock address (00h to 07h). The update will resume either due to a Stop Condition or when the pointer increments to any non-clock address (08h-13h). Clock and Alarm Registers store data in BCD. Calibration, Watchdog and Square Wave Registers store data in Binary Format.
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M41T81S Table 2.
Addr D7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h OUT OFIE AFE RPT4 RPT3 RPT2 RPT1 WDF 0 0 0 RS3 ST 0 CEB 0 0 0 CB 0 0 0 FT BMB4 SQWE RPT5 HT 10 Years S BMB3 ABE BMB2 Al 10M BMB1 D6 D5 0.1 Seconds 10 Seconds 10 Minutes 10 Hours 0 0 0 10M 0 10 Date D4 D3 D2 D1 0.01 Seconds Seconds Minutes Hours (24 Hour Format) Day of Week Date: Day of Month Month Year Calibration BMB0 RB1 RB0 Alarm Month Alarm Date Alarm Hour Alarm Minutes Alarm Seconds 0 0 0 0 0 OF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D0
Clock operation Clock register map
Function/Range BCD Format Seconds Seconds Minutes Century/ Day Date Month Year Calibratio Watchdo Al Month Al Date Al Hour Al Min Al Sec Flags Reserved Reserved Reserved SQW 01-12 01-31 00-23 00-59 00-59 00-99 00-59 00-59 0-1/0001-7 01-31 01-12 00-99
AI 10 Date AI 10 Hour
Alarm 10 Minutes Alarm 10 Seconds AF 0 0 0 RS2 0 0 0 0 RS1 BL 0 0 0 RS0
0 = Must be set to '0' ABE = Alarm in Battery Back-up Mode Enable Bit AF = Alarm Flag (Read only) AFE = Alarm Flag Enable Flag BL = Battery Low Bit BMB0-BMB4 = Watchdog Multiplier Bits CB = Century Bit CEB = Century Enable Bit FT = Frequency Test Bit HT = Halt Update Bit OF = Oscillator Fail Flag OFIE = Oscillator Fail Interrupt Enable OUT = Output level RB0-RB1 = Watchdog Resolution Bits RPT1-RPT5 = Alarm Repeat Mode Bits RS0-RS3 = SQW Frequency S = Sign Bit SQWE = Square Wave Enable ST = Stop Bit WDF = Watchdog Flag (Read only)
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Clock operation
M41T81S
Calibrating the clock
The M41T81S is driven by a quartz controlled oscillator with a nominal frequency of 32,768Hz. The devices are tested not exceed 35 ppm (parts per million) oscillator frequency error at 25oC, which equates to about +1.9 to -1.1 minutes per month (see Figure 11 on page 17). When the Calibration circuit is properly employed, accuracy improves to better than 2 ppm at 25C. The oscillation rate of crystals changes with temperature. The M41T81S design employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 12 on page 17. The number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five Calibration Bits found in the Calibration Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration Bits occupy the five lower order bits (D4-D0) in the Calibration Register 08h. These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register (see Figure 12 on page 17). Assuming that the oscillator is running at exactly 32,768Hz, each of the 31 increments in the Calibration byte would represent +10.7 or -5.35 seconds per month which corresponds to a total range of +5.5 or -2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M41T81S may require. The first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. Calibration values, including the number of seconds lost or gained in a given period, can be found in Application Note AN934, "TIMEKEEPER(R) Calibration." This allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non-user serviceable enclosure. The designer could provide a simple utility that accesses the Calibration byte. The second approach is better suited to a manufacturing environment, and involves the use of the IRQ/FT/OUT/SQW pin. The pin will toggle at 512Hz, when the Stop Bit (ST, D7 of 01h) is '0,' the Frequency Test Bit (FT, D6 of 08h) is '1,' the Alarm Flag Enable Bit (AFE, D7 of 0Ah) is '0,' and the Square Wave Enable Bit (SQWE, D6 of 0Ah) is '0' and the Watchdog Register (09h = 0) is reset. Any deviation from 512Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.010124Hz would indicate a +20 ppm oscillator frequency error, requiring a -10 (XX001010) to be loaded into the Calibration Byte for correction. Note that setting or changing the Calibration Byte does not affect the Frequency Test output frequency.
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M41T81S
Clock operation The IRQ/FT/OUT/SQW pin is an open drain output which requires a pull-up resistor to VCC for proper operation. A 500-10k resistor is recommended in order to control the rise time. The FT Bit is cleared on power-down. Figure 11. Crystal accuracy across temperature
Frequency (ppm) 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 F = K x (T - T )2 O F K = -0.036 ppm/C 0.006 ppm/C TO = 25C 5C
2 2
Temperature C
AI07888
Figure 12. Clock calibration
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
Setting alarm clock registers
Address locations 0Ah-0Eh contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific month, date, hour, minute, or second or repeat every year, month, day, hour, minute, or second. It can also be programmed to go off while the M41T81S is in the battery back-up mode to serve as a system wake-up call. Bits RPT5-RPT1 put the alarm in the repeat mode of operation. Table 3 on page 18 shows the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. When the clock information matches the alarm clock settings based on the match criteria defined by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE (Alarm Flag Enable) is also set (and SQWE is '0.'), the alarm condition activates the IRQ/FT/OUT/SQW pin. Note: If the address pointer is allowed to increment to the Flags Register address, an alarm condition will not cause the Interrupt/Flag to occur until the address pointer is moved to a
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Clock operation
M41T81S
different address. It should also be noted that if the last address written is the "Alarm Seconds," the address pointer will increment to the Flag address, causing this situation to occur. The IRQ/FT/OUT/SQW output is cleared by a READ to the Flags Register as shown in Figure 13. A subsequent READ of the Flags Register is necessary to see that the value of the Alarm Flag has been reset to '0.' The IRQ/FT/OUT/SQW pin can also be activated in the battery back-up mode. The IRQ/FT/OUT/SQW will go low if an alarm occurs and both ABE (Alarm in Battery Back-up Mode Enable) and AFE are set. Figure 14 illustrates the back-up mode alarm timing. Figure 13. Alarm interrupt reset waveform
0Eh 0Fh 10h
ACTIVE FLAG
IRQ/FT/OUT/SQW
HIGH-Z
AI04617
Figure 14. Back-up mode alarm waveform
VCC VPFD VSO trec ABE and AFE Bits AF Bit in Flags Register IRQ/FT/OUT/SQW
HIGH-Z
AI09164b
Table 3.
RPT5 1 1 1 1 1 0
Alarm repeat modes
RPT4 1 1 1 1 0 0 RPT3 1 1 1 0 0 0 RPT2 1 1 0 0 0 0 RPT1 1 0 0 0 0 0 Alarm Setting Once per Second Once per Minute Once per Hour Once per Day Once per Month Once per Year
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the Watchdog Register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order
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M41T81S
Clock operation bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 second, 10 = 1 second, and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of the five-bit multiplier value with the resolution. (For example: writing 00001110 in the Watchdog Register = 3*1, or 3 seconds). If the processor does not reset the timer within the specified period, the M41T81S sets the WDF (Watchdog Flag) and generates a watchdog interrupt. The watchdog timer can be reset by having the microprocessor perform a WRITE of the Watchdog Register. The time-out period then starts over. Should the watchdog timer time-out, a value of 00h needs to be written to the Watchdog Register in order to clear the IRQ/FT/OUT/SQW pin. This will also disable the watchdog function until it is again programmed correctly. A READ of the Flags Register will reset the Watchdog Flag (Bit D7; Register 0Fh). The watchdog function is automatically disabled upon power-up and the Watchdog Register is cleared. If the watchdog function is set, the frequency test function is activated, and the SQWE Bit is '0,' the watchdog function prevails and the frequency test function is denied.
Square wave output
The M41T81S offers the user a programmable square wave function which is output on the SQW pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These frequencies are listed in Table Table 4. Once the selection of the SQW frequency has been completed, the IRQ/FT/OUT/SQW pin can be turned on and off under software control with the Square Wave Enable Bit (SQWE) located in Register 0Ah. Table 4. Square Wave Output Frequency
Square Wave Bits RS3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Square Wave RS0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
RS2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
RS1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Frequency
None 32.768 8.192 4.096 2.048 1.024 512 256 128 64 32 16 8 4 2 1
Units
kHz kHz kHz kHz kHz Hz Hz Hz Hz Hz Hz Hz Hz Hz Hz
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Clock operation
M41T81S
Century bit
Bits D7 and D6 of Clock Register 03h contain the CENTURY ENABLE Bit (CEB) and the CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,' CB will not toggle.
Battery low warning
The M41T81S automatically performs battery voltage monitoring upon power-up and at factory-programmed time intervals of approximately 24 hours. The Battery Low (BL) Bit, Bit D4 of Flags Register 0Fh, will be asserted if the battery voltage is found to be less than approximately 2.5V. The BL Bit will remain asserted until completion of battery replacement and subsequent battery low monitoring tests, either during the next power-up sequence or the next scheduled 24-hour interval. If a battery low is generated during a power-up sequence, this indicates that the battery is below approximately 2.5 volts and may not be able to maintain data integrity. Clock data should be considered suspect and verified as correct. A fresh battery should be installed. If a battery low indication is generated during the 24-hour interval check, this indicates that the battery is near end of life. However, data is not compromised due to the fact that a nominal VCC is supplied. In order to insure data integrity during subsequent periods of battery back-up mode, the battery should be replaced. The M41T81S only monitors the battery when a nominal VCC is applied to the device. Thus applications which require extensive durations in the battery back-up mode should be powered-up periodically (at least once every few months) in order for this technique to be beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon power-up via a checksum or other technique.
Oscillator fail detection
If the Oscillator Fail Bit (OF) is internally set to '1,' this indicates that the oscillator has either stopped, or was stopped for some period of time and can be used to judge the validity of the clock and date data. In the event the OF Bit is found to be set to '1' at any time other than the initial power-up, the STOP Bit (ST) should be written to a '1,' then immediately reset to '0.' This will restart the oscillator. The following conditions can cause the OF Bit to be set:

The first time power is applied (defaults to a '1' on power-up). The voltage present on VCC is insufficient to support oscillation. The ST Bit is set to '1.' External interference of the crystal.
The OF Bit will remain set to '1' until written to logic '0.' The oscillator must start and have run for at least 4 seconds before attempting to reset the OF Bit to '0.'
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M41T81S
Clock operation
Oscillator fail interrupt enable
If the Oscillator Fail Interrupt Bit (OFIE) is set to a '1,' the IRQ pin will also be activated. The IRQ output is cleared by resetting the OFIE or OF Bit to '0' (not be reading the Flags Register).
Output driver pin
When the FT Bit, AFE Bit, SQWE Bit, and Watchdog Register are not set, the IRQ/FT/OUT/SQW pin becomes an output driver that reflects the contents of D7 of the Calibration Register. In other words, when D7 (OUT Bit) and D6 (FT Bit) of address location 08h are a '0,' then the IRQ/FT/OUT/SQW pin will be driven low. Note: The IRQ/FT/OUT/SQW pin is an open drain which requires an external pull-up resistor.
Preferred initial power-on default
Upon initial application of power to the device, the following register bits are set to a '0' state: Watchdog Register; AFE; ABE; SQWE; OFIE; and FT. The following bits are set to a '1' state: ST; OUT; OF; and HT (see Table 5 on page 21). Table 5. Preferred default values
ST 1 UC HT 1 1 Out 1 UC FT 0 0 AFE SQWE ABE 0 UC 0 UC 0 UC WATCHDOG Register(1) 0 0 OF 1 UC OFIE 0 UC
Condition Initial Power-up(2) Subsequent Powerup (with battery back-up)(3)
1. BMB0-BMB4, RB0, RB1 2. State of other control bits undefined 3. UC = Unchanged
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Maximum rating
M41T81S
4
Maximum rating
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 6.
Sym TSTG VCC
Absolute maximum ratings
Parameter Storage Temperature (VCC Off, Oscillator Off) Supply Voltage Lead Solder Temperature for 10 Seconds Input or Output Voltages Output Current Power Dissipation Lead-free lead finish(1) Standard (SnPb) lead finish(2,3) SOIC Value -55 to 125 -0.3 to 7 260 240 -0.3 to Vcc+0.3 20 1 Unit C V C C V mA W
TSLD
VIO IO PD
Note:
For SO8 package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260C (total thermal budget not to exceed 245C for greater than 30 seconds). For SO8 package, standard (SnPb) lead finish: Reflow at peak temperature of 240C (total thermal budget not to exceed 180C for between 90 to 150 seconds). The SOX18 package has Lead-free (Pb-free) lead finish, but cannot be exposed to peak reflow temperature in excess of 240C (use same reflow profile as standard (SnPb) lead finish).
Caution:
Negative undershoots below -0.3 volts are not allowed on any pin while in the Battery Backup Mode
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M41T81S
DC and AC parameters
5
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measurement Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 7. Operating and AC measurement conditions
Parameter Supply Voltage (VCC) Ambient Operating Temperature (TA) Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages M41T81S 2.7 to 5.5V -40 to 85C 100pF 50ns 0.2VCC to 0.8 VCC 0.3VCC to 0.7 VCC
Note:
Output Hi-Z is defined as the point where data is no longer driven. Figure 15. AC measurement I/O waveform
0.8VCC
0.7VCC 0.3VCC
AI02568
0.2VCC
Table 8.
Symbol CIN COUT(3) tLP
Capacitance
Parameter(1) and (2) Input Capacitance Output Capacitance Low-pass filter input time constant (SDA and SCL) Min Max 7 10 50 Unit pF pF ns
1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested. 2. At 25C, f = 1MHz 3. Outputs deselected
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DC and AC parameters Table 9.
Sym ILI ILO ICC1
M41T81S DC characteristics
Parameter Test Condition(1) 0V VIN VCC 0V VOUT VCC Switch Freq = 400kHz SCL = 0Hz All Inputs VCC - 0.2V VSS + 0.2V -0.3 0.7VCC IOL = 3.0mA IOL = 10mA IRQ/OUT/FT/SQW 2.0 TA = 25C, VCC = 0V Oscillator ON, VBAT = 3V 0.6 Min Typ Max 1 1 400 Unit A A A
Input Leakage Current Output Leakage Current Supply Current
ICC2
Supply Current (standby)
100
A
VIL VIH
Input Low Voltage Input High Voltage Output Low Voltage
0.3VCC VCC + 0.3 0.4 0.4 5.5 3.5(4) 1
V V V V V V A
VOL
Output Low Voltage (Open Drain)(2) Pull-up Supply Voltage (Open Drain)
VBAT(3) IBAT
Back-up Supply Voltage Battery Supply Current
1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 2.7 to 5.5V (except where noted). 2. For IRQ/FT/OUT/SQW pin (open drain) 3. STMicroelectronics recommends the RAYOVAC BR1225 or BR1632 (or equivalent) as the battery supply. 4. For rechargeable back-up, VBAT (max) may be considered to be VCC.
Table 10.
Sym fO RS CL
Crystal electrical characteristics
Parameter(1)and(2) Resonant Frequency Series Resistance Load Capacitance 12.5 Min Typ 32.768 Max 60(3) Units kHz k pF
1. Externally supplied if using the SO8 package. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp for further information on this crystal type. 2. Load capacitors are integrated within the M41T81S. Circuit board layout considerations for the 32.768kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account. 3. For applications requiring back-up supply operation below 2.5V, RS (max) should be considered 40k.
Figure 16. Power down/up mode AC waveforms
VCC VSO tPD SDA SCL DON'T CARE
AI00596
trec
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M41T81S Table 11.
Symbol tPD trec
DC and AC parameters Power down/up AC characteristics
Parameter(1)and(2) SCL and SDA at VIH before Power Down SCL and SDA at VIH after Power Up Min 0 10 Typ Max Unit nS S
1. VCC fall time should not exceed 5mV/s. 2. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 2.7 to 5.5V (except where noted).
Table 12.
Sym VPFD
Power down/up trip points DC characteristics
Parameter(1)and(2) Min 2.5 Typ 2.6 25 VBAT VPFD 40 Max 2.7 Unit V mV V V mV
Power-fail Deselect Hysteresis VBAT < Battery Back-up Switchover Voltage VPFD (VCC < VBAT; VCC < VPFD) VBAT > VPFD Hysteresis
VSO
1. All voltages referenced to VSS. 2. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 2.7 to 5.5V (except where noted).
Figure 17. Bus timing requirements sequence
SDA tBUF tHD:STA tR SCL tHIGH P S tLOW tSU:DAT tHD:DAT tSU:STA SR P tSU:STO tF tHD:STA
AI00589
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DC and AC parameters Table 13.
Sym fSCL tLOW tHIGH tR tF tHD:STA
M41T81S AC characteristics
Parameter(1) SCL Clock Frequency Clock Low Period Clock High Period SDA and SCL Rise Time SDA and SCL Fall Time START Condition Hold Time (after this period the first clock pulse is generated) START Condition Setup Time (only relevant for a repeated start condition) Data Setup Time Data Hold Time STOP Condition Setup Time Time the bus must be free before a new transmission can start 600 Min 0 1.3 600 300 300 Typ Max 400 Units kHz s ns ns ns ns
tSU:STA tSU:DAT tHD:DAT
(2)
600 100 0 600 1.3
ns ns s ns s
tSU:STO tBUF
1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 2.7 to 5.5V (except where noted). 2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL.
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M41T81S
Package mechanical data
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 18. SO8 - 8-lead plastic small package outline
h x 45 A2 b e 0.25 mm GAUGE PLANE k
8
A ccc c
D
E1
1
E A1 L L1
SO-A
Note:
Drawing is not to scale. Table 14. SO8 - 8-lead plastic small outline (150 mils body width), package mechanical data
Symb Typ A A1 A2 b c ccc D E E1 e h k L L1 1.04 4.90 6.00 3.90 1.27 0.25 0 0.40 0.50 8 0.127 0.041 4.80 5.80 3.80 0.10 1.25 0.28 0.17 0.48 0.23 0.10 5.00 6.20 4.00 0.193 0.236 0.154 0.050 0.010 0 0.016 0.020 8 0.050 0.189 0.228 0.150 mm Min Max 1.75 0.25 Typ inches Min 0.004 0.049 0.011 0.007 0.019 0.009 0.004 0.197 0.244 0.157 Max 0.069 0.010
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Package mechanical data
M41T81S
Figure 19. SOx18 - 18-lead plastic small outline, 300mils, embedded crystal, outline
Note:
Drawing is not to scale. Table 15. SOX18 - 18-lead plastic small outline, 300mils, embedded crystal, package mechanical data
millimeters Symbol Typ A A1 A2 B c D E E1 e L 2.57 0.23 2.34 0.46 0.25 11.61 7.62 10.34 1.27 0.66 0.51 0.81 Min 2.44 0.15 2.29 0.41 0.20 11.56 7.57 10.16 Max 2.69 0.31 2.39 0.51 0.31 11.66 7.67 10.52 Typ 0.101 0.009 0.092 0.018 0.010 0.457 0.300 0.407 0.050 0.026 0.020 0.032 Min 0.096 0.006 0.090 0.016 0.008 0.455 0.298 0.400 Max 0.106 0.012 0.094 0.020 0.012 0.459 0.302 0.414 inches
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M41T81S
Part numbering
7
Part numbering
Table 16.
Example:
Ordering information
M41T 81S M 6 E
Device Type M41T
Supply Voltage and Write Protect Voltage 81S = VCC = 2.7 to 5.5V
Package M = SO8 MY(1) = SOX18
Temperature Range 6 = -40C to 85C
Shipping Method For SO8: E = ECOPACK Package, Tubes F = ECOPACK Package, Tape & Reel For SOX18: blank = ECOPACK Package, Tubes T = ECOPACK Package, Tape & Reel
Note:
The SOX18 package includes an embedded 32,768Hz crystal. Contact local ST sales office for availability. For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you.
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Revision history
M41T81S
8
Date
Revision history
Version 0.1 0.2 0.3 1.0 1.1 1.2 2.0 3.0 4.0 5.0 First Draft Update BL information, characteristics, ratings, and Lead (Pb)-free information (Table 12, Table 6, Table 10, Table 16) Update characteristics (Table 11, Table 12, Table 7, Part numbering) Product promoted; reformatted; update characteristics, including Lead-free package information (Figure 3, Figure 4, Figure 11, Figure 14; Table 4, Table 13, Table 16) Update DC Characteristics (Table 9) Add shipping package ( Table 16) Update maximum ratings (Table 6) Promote document; update characteristics and marketing status (cover page, Figure 5; Table 16) Update features; added Lead-free information (cover page; Figure 4; Table 16) Remove TIMEKEEPER references and update package mechanical data (Figure 18, Table 14 and Figure 19, Table 15) Revision Details
22-Jan-2004 06-Feb-2004 20-Feb-2004 14-Apr-2004 05-May-2004 16-Jun-2004 13-Sep-2004 26-Nov-2004 23-Sep-2005 22-Jan-2007
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M41T81S
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